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W83759A ADVANCED VL-IDE DISK CONTROLLER
GENERAL DESCRIPTION
The W83759A is an advanced version of Winbond's popular VL-IDE interface chip, the W83759. The W83759A retains all of the features and compatibility of the W83759 (the chip meets the ANSI ATA 4.0 specification for IDE hard disk operation and the VESA VL-Bus 2.0 specification for PC local bus devices) while incorporating new features to meet Enhanced IDE, SFF-8011, ATA-2, and Fast-ATA specifications.
Supports Disk Capacity of Greater than 528 MB
The W83759A's driver can handle remapping from BIOS CHS mode to HDD LBA mode. This scheme enables users to break the 528 MB per drive barrier, allowing full use of BIOS INT13 CHS information in drives with a capacity of up to 8.4 GB.
High Speed Host Transfer Rate
The W83759A supports Enhanced IDE PIO mode 3 and Fast ATA PIO mode 3 and 4 timing; jumper settings or driver programming can be used to select the PIO mode and a 33 or 50 MHz VL-Bus clock. Different programming timing can be selected for different drives in the same system. The burst transfer rate is shown in the following table. ATA PIO MODE 0 1 2 3 4 IDE COMMAND CYCLE TIME (nS) 600 383 240 180 120 BURST TRANSFER RATE (MB/sec) 3.33 5.22 8.33 11.1 16.6 IORDY THROTTLE CONTROL Option Option Option Required Required
Dual IDE Channels
Like the W83759, the W83759A supports a secondary IDE address (170h-177h/376h) and IRQ15 for applications with four hard disk drives. Additionally, the primary and secondary channels can be independently enabled or disabled by jumper settings or software programming.
Non-disk IDE Peripherals
Because the command cycle can be programmed individually for each drive and dual IDE channels are supported, non-disk IDE peripherals (such as an ATAPI CD-ROM or tape drive) can be attached to the secondary IDE without affecting the transfer rate of the ATA disk drive. Sales of ATAPI IDE CD-ROMs are expected to grow rapidly as these devices become a standard part of many users' desktop PC setup.
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Publication Release Date: May 1995 Revision A1
W83759A
Enhanced IDE/Fast ATA Dual Channel Structure
Primary Channel 40-pins Secondary Channel 40-pins
Disk < 8.4 GB
Disk < 8.4 GB
CD ROM ATAPI
Tape ATAPI
PD0
PD1
SD0
SD1
The W83759A provides all of the next-generation ATA-IDE requirements, including support for high capacity disk drives, high speed host transfers, multiple IDE peripherals, and non-disk IDE peripherals. It makes high-performance, low-cost, easy-to-use IDE machines possible. The W83759A is pin-to-pin backward compatible with the W83759. In addition to the advanced features described above, the W83759A supports automatic power-down, standby, and suspend APM power management states for green PC applications. This new chip is packaged in a 100-pin QFP. The table below compares the W83759 and W83759A: W83759 Dual Channel IDE 8.4 G Max. Cap. PIO Mode 3, 4 Control DMA Mode Control IOCHRDY Control IDE Timing Control Prefetch Control Power Saving Control ATAPI Protocol
* All control is drive-by-drive (per drive selectability)
W83759A Yes Software Driving Yes* Yes* Yes* Jumper or Driver* Yes* Yes* Software Driving
Yes Software Driving No No No Jumper No No Software Driving
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W83759A
FEATURES
* * * * * * * * * * * * * * * * *
Pin-to-pin backward compatible with W83759 VL-IDE Interface chip VESA VL-Bus Rev 2.0 compatible, connects directly to local bus and four IDE drives Direct interface to various ANSI ATA/ATA-2/FAST ATA/IDE-2/Enhanced IDE drives Supports 32 and 16-bit data transfer Fully software programmable for command active/recovery time and address setup, data hold time Built-in VL-Bus to 16-bit IO data buffer for special applications Fully supports Enhanced IDE features, including Fast PIO, Mode 3/4, IORDY flow control, prefetch control Supports dual channels to allow up to four drives or non-disk devices (ATAPI CD-ROM and tape drives) Pipeline pre-fetched reads and posted writes for concurrent disk and host operations Independent access timing for all drives (primary/secondary and master/slave) All Enhanced IDE new features may be disabled/enabled via driver or power-on setting by per drive selectability ATA/Mode 0-4 PIO speed may be set as default timing of each drive via power-on jumper setting Supports slave DMA mode protocol (reserved) Supports auto power-down, standby, suspend APM power management state for green PCs Primary and secondary channel can be independently enabled/disabled by software or jumper setting Supports drivers for DOS, Windows, OS/2, UNIX, and Netware Packaged in 100-pin QFP
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Publication Release Date: May 1995 Revision A1
W83759A
PIN CONFIGURATION
I D D 7
Sa mp le Te xt
I D D 8
Sa m pl e Te xt
I D D 9
Sa mp le Te xt
I D D 1 0
Sa mpl e Tex t
I D D 1 1
Sa mpl e Tex t
I D D 1 2
Sa mp le Te xt
I D D 1 3
Sa mpl e Tex t
I D D 1 4
Sa mpl e Tex t
I D D 1 5
Sa mpl e Tex t
/ I D E I O W
Sa mp le Te xt
/ I D E I O R
Sa mpl e Tex t
I D E A 2 , M D 1
Sa mp le Te xt
I D E A 1 , M D 0
Sa mpl e Tex t
T E S T , I / D I E D A E 0 1 , SGVC PNcS 1Dc1
Sa mp le Te xt Sa mp le Te xt X X
E N I D E , / I D E 1 C S 0
X
/ I D E 0 C S 1
X
/ I D E 0 C S 0
X
/ I S D E N H , / V G A O E L
X
/ D A C K , / V G A OSSSSSSSS EDDDDDDDD H7654321 0
X X X X X X X X X
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 IDD6 IDD5 IDD4 IDD3 IDD2 IDD1 IDD0 GND LCLK GND Vcc LDEV LRDY RDYRTN LADS HWR HMIO IORDY/HDC SYSRST ADV
X
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 123456
Sa mp le Te xt Sa m pl e Te xt Sa mp le Te xt Sa mpl e Tex t Sa mpl e Tex t Sa mp le Te xt
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Sa mpl e Tex t Sa mpl e Tex t Sa mpl e Tex t Sa mp le Te xt Sa mpl e Tex t Sa mp le Te xt Sa mpl e Tex t Sa mp le Te xt Sa mp le Te xt
X
AEN XIOW XIOR SA1 SA0 HD0 HD1 HD2 HD3 Vcc GND HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
/ B E 2
/ HHHHHH HHH H BAAAAAA AADD E2345678933 0 10
H D 2 9
HGHHH DNDDD 2D222 765 8
H D 2 4
H D 2 3
H D 2 2
H D 2 1
H D 2 0
H D 1 9
H D 1 8
H D 1 7
H D 1 6
H D 1 5
H D 1 4
H D 1 3
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W83759A
PIN DESCRIPTION
SYMBOL ADV PIN 100 TYPE I-PU DESCRIPTION VL-Bus Interface Advanced mode indicator. When high, chip is in W83759A mode. When low, chip is in W83759 mode. VL-Bus clock. System reset. When active, the power-on setting pin acts as input. Address data strobe. An active low input signal indicates that there is a valid address and command on the bus. In W83759A mode: Enhanced IDE IORDY flow control input. Used to throttle disk's PIO data transfers to improve PIO mode. In W83759 mode: Host data or code status. Used to distinguish between IO and interrupt or halt cycles. Host memory or I/O status. Used to distinguish between memory and I/O cycles. Host write or read status. Used to distinguish between write and read cycles. Byte enable bits 2 and 0 from the host CPU address bus. These active low inputs specify which bytes will be valid for host read and write data transfers. When BE2 is low, the host performs a 32-bit hard disk data transfer cycle when LDEV is active. Local device. An active low output signal which indicates that the current host CPU command cycle is a valid W83759A I/O address (1F0h or 170h). Local ready. An active low output that indicates when a CPU transfer has been completed. During a cycle LRDY will first be enabled and driven high. When the cycle is completed, LRDY will immediately be pulled low and will remain active for one T-state. Then it will drive high for one T-state before finally being disabled to end the sequence. This signal is shared with all other VL-Bus targets and driven by W83759A only during cycles W83759A has claimed as its own.
LCLK
SYSRST LADS
89 99 95
I I I
IORDY / HDC
98
I
HMIO HWR BE2 BE0
97 96 1 2
I-PU I I
LDEV
92
O
LRDY
93
Tri-O
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Publication Release Date: May 1995 Revision A1
W83759A
Pin Description, continued
SYMBOL
RDYRTN
PIN 94
TYPE I
DESCRIPTION Ready return. An active low signal that indicates the end of the current host CPU transfer. Usually RDYRTN is tied directly to the RDY signal of the host CPU. Host address bits 9 through 2 from the host address bus. Host data. This is the 32-bit bidirectional data bus that connects to the host CPU. HD[7:0] define the lowest data byte, while D[31:24] define the most significant byte by the BE[2:0] signals. The HD bus is normally in a high-impedance state and is driven by the W83759A only during data register (1F0h or 170h) read cycles and VGA ( VGAOEH = 0 or VGAOEL = 0) read cycles. Drive Interface
HA[9:2] HD[31:0]
10-3 11-14 19-39 42-45
I I/O
PRDYEN / IDE0CS0
61
I/O -PU
When SYSRST is active, this is an input that latches on the rising edge of SYSRST . PRDYEN: A high input enables the IORDY flow control function of the primary channel (IDE0) and a low input disables the IDE0's flow control function.
IDE0CS0 : When SYSRST is inactive, this pin is an active low output used to select the command block registers in the IDE0 drive (1F0h-1F7h).
SRDYEN / IDE0CS1
62
I/O -PU
When SYSRST is active, this is an input that latches on the rising edge of SYSRST . SRDYEN: A high input enables the IORDY flow control function of the secondary channel (IDE1) and a low disables the IDE1's flow control function.
IDE0CS1: When SYSRST is inactive, this pin is an active low output used to select the alternate status register of the control block registers in the IDE0 drive (3F6).
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W83759A
Pin Description, continued
SYMBOL ENIDE / IDE1CS0
PIN 63
TYPE I/O -PU
DESCRIPTION When SYSRST is active, this is an input that latches on the rising edge of SYSRST . ENIDE: In W83759 mode (ADV = low), this power-on-setting pin controls if the chip enable or disable. In W83759A mode (ADV = high), this pin controls if the IDE0 channel enable or disable. A high input enables and a low input disables the IDE0 channel.
IDE1CS0 : When SYSRST is inactive, this pin is an active low output and is used to select the command block registers in the IDE1 drive (170h-177h).
TEST / IDE1CS1
64
I/O -PU
When SYSRST is active, this is an input that latches on the rising edge of SYSRST . TEST: In W83759 mode, this power-on-setting pin controls whether both dual channels are enabled or only the primary channel is enabled. A high input enables IDE0 and IDE1 simultaneously and a low input enables IDE0 only. In W83759A mode, this pin controls whether the IDE1 channel enable or disable controls the IDE0 channel as ENIDE.
IDE1CS1: When SYSRST is inactive, this pin is an active low output used to select the alternate status register of the control block registers in the IDE1 drive (376).
EMD1 / IDEIOR
70
I/O -PU
When SYSRST is active, this is an input that latches on the rising edge of SYSRST . EMD1: This power-on-setting pin combines with EMD0 to set the initial enhanced timing mode of hard disk access cycles when the enhanced mode is selected via the POSS3 configuration register.
IDEIOR : Drive I/O read. An active low output that enables data to be read from the drive. The duration and repetition rate of IDEIOR cycles are determined by the type of IDE drive, as specified by MD1 and MD0, in W83759 mode or by EMD1 and EMD0 in W83759A enhanced mode.
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Publication Release Date: May 1995 Revision A1
W83759A
Pin Description, continued
SYMBOL EMD0 / IDEIOW
PIN 71
TYPE I/O -PU
DESCRIPTION When SYSRST is active, this is an input that latches on the rising edge of SYSRST . EMD0 : This power-on-setting pin combines with EMD1 to set the initial enhanced timing mode of hard disk access cycles when the enhanced mode is selected via the POSS3 configuration register.
ATA PIO mode 2 3 3 4 Access Time 240 nS 180 nS 180 nS 120 nS EMD1 1 1 0 0 EMD0 1 0 1 0
IDEIOW : Drive I/O write. An active low output that enables data to be written to the drive. The duration and repetition rate of IDEIOW cycles are determined by the type of IDE drive, as specified by IDEIOR.
MD1 /IDEA2, MD0 /IDEA1
69 68
I/O -PD
When SYSRST is active, these pins function as inputs and latch on the rising edge of SYSRST . MD1, MD0: ATA mode of IDE Drive. MD0 and MD1 are used to select the hard disk access time.
ATA PIO mode 0 0+ 1 2 Access Time 600 nS 500 nS 400 nS 240 nS EMD1 0 0 1 1 EMD0 0 1 0 1
IDEA2, IDEA1: IDE drive address bits 2 and 1. Drive address bits 2 and 1 are outputs to the IDE connector for register selection in the drive.
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W83759A
Pin Description, continued
SYMBOL SP1 /IDEA0
PIN 67
TYPE I/O -PD
DESCRIPTION When SYSRST is active, this pin is an input that latches on the rising edge of SYSRST . SP1: VL-Bus speed select. A high input configures the W83759A to run at from 33 MHz to 50 MHz; a low input configures the W83759A to run at under 33 MHz. IDEA0: IDE drive address bit 0. Drive address bit 0 is output to the IDE connector for register selection in the drive.
IDD[15:0]
72-87
I/O -PU
When SYSRST is active, these pins function as inputs and latch on the rising edge of SYSRST . As power-on setting pins, IDD[15:8] are latched to the POSS3 register and IDD[7:0] are latched to the POSS2 register. As the drive data bus, bits 15 through 0 are the 16-bit bidirectional data bus that connects to the IDE drive. IDD[7:0] define the lowest data byte. The IDD bus is normally in a pull-high state and is driven with valid data by the W83759A only during IDE or VGA ( VGAOEH = 0 or VGAOEL = 0) write cycles. ISA-Bus Interface
SA[1:0] SD[7:0]
47, 46 58-51
I I/O
ISA address bits 1 and 0. Used to select the hard disk I/O registers. These signals provide data bus bits 0 through 7 for the CPU and IDE I/O devices. SD0 is the least significant bit and SD7 is the most significant bit.
XIOR instructs the hard disk I/O device to drive its data onto the SD data bus. XIOW instructs the hard disk I/O device to read the data on the SD data bus.
XIOR XIOW
48 49 50
I I I
AEN
When this line is active (high), the DMA controller has control of the address bus. A low is the address enable.
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Publication Release Date: May 1995 Revision A1
W83759A
Pin Description, continued
SYMBOL
PIN 59
TYPE I-PU
DESCRIPTION Special Bus Control Interface This pin is a multi-function input pin. SUSP : In suspend enable mode, indicates that the W83759A will enter the suspend state when low and resume operation when high. DACK : In DMA transfer enable mode, used to indicate when the DMA transfer cycle occurs. VGAOEH : In VGA buffer enable mode, this active low input controls the input enable for the data transceivers that connect the ID[15:0] pins to the HD[31:16] pins.
SUSP , DACK , VGAOEH
DMASL , VGAOEL / ISDENH
60
I/O -PU
When SYSRST is active, this pin is an input that latches on the rising edge of SYSRST . DMASL : This power-on setting pin combines with SUSPEN (IDD11 power-on setting pin) to determine which mode the W83759A is in.
DMASL 1 0 0 SUSPEN X 1 0 Mode VGA buffer enable Suspend enable DMA transfer enable
VGAOEL : In VGA buffer enable mode, this active low input controls the input enable for the data transceivers that connect the ID[15:0] pins to the HD[15:0] pins. ISDENH : In DMA transfer enable mode, this output pin controls the activity of the high byte buffer between IDD[15:8] and SD[15:8]. Vcc GND 41, 65, 91 15, 40, 66, 88, 90 +5V power supply Ground reference
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W83759A
CONFIGURATION REGISTERS
Several configuration registers are implemented in the W83759A. These registers are accessible in single-chip mode through the index/data port. The index/data port address is 1B4h/1B8h or 134h/138h, depending on whether pin IDD0 is high or low at power-on. When the W83759A is in multi-chip mode (IDD1 is low at power-on setting), an ID code should be written to 1B0h/130h (IDIN port). The W83759A will then enter the programming sequence if the ID code matches the chip ID (determined by IDD2, IDD3 at power-on setting) or leave the programming sequence if the ID code does not match. After the chip has entered the programming sequence, the chip ID can be read by reading 1BCh/13Ch (IDOUT port). IDD0_P is HIGH IDIN port (W/O) Index port (R/W) data port (R/W) IDOUT port (R/O) 1B0h* 1B4h 1B8h 1BCh IDD0_P is LOW 130h** 134h 138h 13Ch
* The alias base addresses of 1B0h are XB0h and YB0h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D. ** The alias base addresses of 130h are X30h and Y30h, where "X" means 0, 4, 8, C and "Y" means 1, 5, 9, D.
Index map of configuration registers:
INDEX 80h(R/O) POSS1 81h(R/W) POSP1 82h(R/O) POSS2 83h(R/W) POSP2 84h(R/O) POSS3 85h(R/W) POSP3 86h(R/W) ALTCTL 87h(R/O) REVID 88h(R/W) PD0TIM0 89h(R/W) PD0TIM1 8Ah(R/W) PD1TIM0 8Bh(R/W) PD1TIM1 8Ch(R/W) SD0TIM0 8Dh(R/W) SD0TIM1 8Eh(R/W) SD1TIM0 8Fh(R/W) SD1TIM1 Bit 7 ADV ADV_P PD0LEN PD0LE_P PD0EM# PD0EM#_P DMASL#_ P DMASL# PD0ACT3 PD0AST1 PD1ACT3 PD1AST1 SD0ACT3 SD0AST1 SD1ACT3 SD1AST1 Bit 6 SP1 SP1_P PD1LEN PD1LEN_P PD1EM# PD1EM#_P Reserved Reserved PD0ACT2 PD0AST0 PD1ACT2 PD1AST0 SD0ACT2 SD0AST0 SD1ACT2 SD1AST0 Bit 5 MD1 MD1_P SD0LEN SD0LEN_P SD0EM# SD0EM#_P EMD1 PDRV PD0ACT1 PD0DHT1 PD1ACT1 PD1DHT1 SD0ACT1 SD0DHT1 SD1ACT1 SD1DHT1 Bit 4 MD0 MD0_P SD1LEN SD1LEN_P SD1EM# SD1EM#_P EMD0 SDRV PD0ACT0 PD0DHT0 PD1ACT0 PD1DHT0 SD0ACT0 SD0DHT0 SD1ACT0 SD1DHT0 Bit 3 PRDYEN PRDYEN_P DSL1 DSL1_P SUSPEN SUSPEN_P PEMD1_P Rev 3 PD0RCV3 PD0PRE# PD1RCV3 PD1PRE# SD0RCV3 SD0PRE# SD1RCV3 SD1PRE# Bit 2 SRDYEN SRDYEN_P DSL0 DSL0_P STBY# STBY#_P PEMD0_P Rev 2 PD0RCV2 PD0DMA# PD1RCV2 PD1DMA# SD0RCV2 SD0DMA# SD1RCV2 SD1DMA# Bit 1 IDEN1 IDEN1_P CRLK# CRLK#_P APD APD_P SEMD1_P Rev 1 PD0RCV1 PD0RDY# PD1RCV1 PD1RDY# SD0RCV1 SD0RDY# SD1RCV1 SD1RDY# Bit 0 IDEN0 IDEN0_P CRSL CRSL_P SWAP# SWAP#_P SEMD0_P Rev 0 PD0RCV0 PD0ADV PD1RCV0 PD1ADV SD0RCV0 SD0ADV SD1RCV0 SD1ADV Default Value 8Fh 8Fh FFh FFh FFh FFh 80h 8Ah 00h 00h 00h 00h 00h 00h 00h 00h
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Publication Release Date: May 1995 Revision A1
W83759A
CRX80h (POSS1) Bit7 ADV Bit 7 Bit6 SP1
Read Only Bit5 MD1 ADV 0 1
Power-on Setting Status 1 Bit4 MD0 Bit3 PRDYEN Bit2 SRDYEN Bit1 IDEN1 Bit0 IDEN0
Power-on setting value of ADV pin Initial application mode No advanced mode application Advanced mode application Power-on setting value of IDEA0 pin Select VESA bus operating CLK VLCLK 33 MHz VLCLK > 33 MHz Power-on setting value of IDEA2, IDEA1 pin Default HDD host transfer mode MD1 MD0 0 0 1 1 0 1 0 1 Mode 0 (cycle time = 600 nS) Mode 0+ (cycle time = 500 nS) Mode 1 (cycle time = 400 nS) Mode 2 (cycle time = 240 nS)
Bit 6
SP1 0 1
Bit 5, 4 MD1, MD0
Bit 3
PRDYEN
Power-on setting value of IDE0CS0 pin Initial state of primary channel IOCHRDY flow control 0 1 Disable IOCHRDY flow control Enable IOCHRDY flow control
Bit 2
SRDYEN
Power-on setting value of IDE0CS1 pin Initial state of secondary channel IOCHRDY flow control 0 1 Disable IOCHRDY flow control Enable IOCHRDY flow control
Bit 1, 0
IDEN1, IDEN0 when ADV_P =0
Power-on setting value of IDE1CS1, IDE1CS0 pins Initial state of IDE ENable control IDEN1 X 0 1 IDEN0 0 1 1 Primary IDE disabled enabled enabled Secondary IDE disabled disabled enabled
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W83759A
Continued
when ADV_P =1
IDEN1 0 1 0 1
IDEN0 0 0 1 1
Primary IDE disabled disabled enabled enabled
Secondary IDE disabled enabled disabled enabled
CRX81h (POSP1) Bit 7 ADV_P Bit 6 SP1_P
Read / Write Bit 5 MD1_P Bit 4 MD0_P Bit 3
Power-on Setting Programming 1 Bit 2 SRDYEN_P Bit 1 IDEN1_P Bit 0 IDEN0_P
PRDYEN_P
After power-on, the content of the POSP1 register is equal to that of the POSS1 register. The host can program POSP1 to modify the power-on settings. Bit 7 ADV_P Programming application mode 0 1 Bit 6 SP1_P No advanced mode application Advanced mode application
Select VESA bus operating CLK 0 1 VLCLK 33 MHz VLCLK > 33 MHz
Bit 5, 4
MD1_P, MD0_P
Select default HDD host transfer mode MD1_P MD0_P 0 0 1 1 0 1 0 1 Mode 0 Mode 1 Mode 2 (cycle time = 600 nS) (cycle time = 400 nS) (cycle time = 240 nS) Mode 0+ (cycle time = 500 nS)
Bit 3
PRDYEN_P
Primary channel IOCHRDY flow control 0 1 Disable IOCHRDY flow control Enable IOCHRDY flow control
Bit 2
SRDYEN_P
Secondary channel IOCHRDY flow control 0 1 Disable IOCHRDY flow control Enable IOCHRDY flow control
Bit 1, 0
IDEN1_P, IDEN0_P
IDE ENable control
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Publication Release Date: May 1995 Revision A1
W83759A
Continued
when ADV_P =0
IDEN1_P X 0 1
IDEN0_P 0 1 1 IDEN0_P 0 0 1 1
Primary IDE disabled enabled enabled Primary IDE disabled disabled enabled enabled
Secondary IDE disabled disabled enabled Secondary IDE disabled enabled disabled enabled
when ADV_P =1
IDEN1_P 0 1 0 1
CRX82h (POSS2) Bit 7 PD0LEN Bit 7 Bit 6 PD1LEN
Read Only Bit 5 SD0LEN PD0LEN Bit 4 SD1LEN
Power-on Setting Status 2 Bit 3 DSL1 Bit 2 DSL0 Bit 1
CRLK
Bit 0 CRSL
Power-on setting value of IDD7 pin Initial Primary Drive 0 (PD0) local device control 0 1 Disable local device Enable local device
Bit 6
PD1LEN
Power-on setting value of IDD6 pin Initial Primary Drive 1 (PD1) local device control 0 1 Disable local device Enable local device
Bit 5
SD0LEN
Power-on setting value of IDD5 pin Initial Secondary Drive 0 (SD0) local device control 0 1 Disable local device Enable local device
Bit 4
SD1LEN
Power-on setting value of IDD4 pin Initial Secondary Drive 1 (SD1) local device control 0 1 Disable local device Enable local device
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W83759A
Continued
Bit 3, 2
DSL1, 0
Power-on setting value of IDD3, IDD2 pin Initial Device ID selection (used in multi-chip mode or CR protection scheme) DSL1 0 0 1 1 DSL0 0 1 0 1 Device ID 60h 61h 62h 63h
Bit 1
CRLK
Power-on setting value of IDD1 pin Initial Configuration Register locked control 0 1 CR is auto-locked (used in multi-chip mode) CR is not auto-locked (used in single-chip mode)
Bit 0
CRSL
Power-on setting value of IDD0 pin Initial Configuration Register selection 0 1 CR port address: 130h, 134h, 138h, 13Ch CR portaddress: 1B0h, 1B4h, 1B8h, 1BCh
CRX83h (POSP2) Bit 7 PD0LEN_ P Bit 6 PD1LEN_ P
Read / Write Bit 5 SD0LEN_P Bit 4 SD1LEN_P
Power-on Setting Programming 2 Bit 3 DSL1_P Bit 2 DSL0_P Bit 1
CRLK _P
Bit 0 CRSL_P
After power-on, the content of the POSP2 register is equal to that of the POSS2 register. The host can program POSP2 to modify the power-on settings. Bit 7 PD0LEN_P Primary Drive 0 (PD0) local device control 0 1 Bit 6 PD1LEN_P Disable local device Enable local device
Primary Drive 1 (PD1) local device control 0 1 Disable local device Enable local device
Bit 5
SD0LEN_P
Secondary Drive 0 (SD0) local device control 0 1 Disable local device Enable local device
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Publication Release Date: May 1995 Revision A1
W83759A
Continued
Bit 4
SD1LEN_P
Secondary Drive 1(SD1) local device control 0 1 Disable local device Enable local device
Bit 3, 2
DSL1, 0_P
Device ID selection (used in multi-chip mode or CR protection scheme) DSL1_P 0 0 1 1 DSL0_P 0 1 0 1 Device ID 60h 61h 62h 63h
Bit 1
CRLK _P
Configuration Register locked control 0 1 CR is auto-locked (multi-chip mode) CR is not auto-locked (single-chip mode)
Bit 0
CRSL_P
Configuration Register selection 0 1 CR port address: 130h, 134h, 138h, 13Ch CR port address: 1B0h, 1B4h, 1B8h, 1BCh
CRX84h (POSS3) Bit 7
PD0EM
Read Only Bit 5
SD0EM PD0EM
Power-on Setting Status 3 Bit 4
SD1EM
Bit 6
PD1EM
Bit 3 SUSPEN
Bit 2 STBY#
Bit 1 APD
Bit 0
SWAP
Bit 7
Power-on setting value of IDD15 pin Initial setting of PD0 enhanced timing enable 0 1 Enhanced timing Programmable timing
Bit 6
PD1EM
Power-on setting value of IDD14 pin Initial setting of PD1 enhanced timing enable 0 1 Enhanced timing Programmable timing
Bit 5
SD0EM
Power-on setting value of IDD13 pin Initial setting of SD0 enhanced timing enable 0 1 Enhanced timing Programmable timing
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W83759A
Continued
Bit 4
SD1EM
Power-on setting value of IDD12 pin Initial setting of SD1 enhanced timing enable 0 1 Enhanced timing Programmable timing
Bit 3
SUSPEN
Power-on setting value of IDD11 pin Initial setting of SUSPend function 0 1 Support DMA mode if DMASL _P = 0 and ADV_P = 1 Support suspend function if DMASL _P = 0 and ADV_P = 1.
Bit 2
STBY
Power-on setting value of IDD10 pin Initial setting of STandBy state 0 1 W83759A is in standby state W83759A is in normal state
Bit 1
APD
Power-on setting value of IDD9 pin Initial setting of auto Power-down 0 1 Auto power-down off Auto power-down on
Bit 0
SWAP
Power-on setting value of IDD8 pin Initial primary, secondary channel connection select 0 1 Primary channel connect to IDE1 Secondary channel connect to IDE0 Primary channel connect to IDE0 Secondary channel connect to IDE1
CRX85h (POSP3)
Bit 7
PD0EM _P
Read/ Write
Bit 5
SD0EM _P
Power-on Setting Programming 3
Bit 4
SD1EM _P
Bit 6
PD1EM _P
Bit 3 SUSPEN_P
Bit 2
STBY _P
Bit 1 APD_P
Bit 0
SWAP _P
Bit 7
PD0EM _P
Power-on setting programming of IDD15 pin Programmable setting of PD0 enhanced timing enable 0 1 Enhanced timing Programmable timing
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Publication Release Date: May 1995 Revision A1
W83759A
Continued
Bit 6
PD1EM _P
Power-on setting programming of IDD14 pin Programmable setting of PD1 enhanced timing enable 0 1 Enhanced timing Programmable timing
Bit 5
SD0EM _P
Power-on setting programming of IDD13 pin Programmable setting of SD0 enhanced timing enable 0 1 Enhanced timing Programmable timing
Bit 4
SD1EM _P
Power-on setting programming of IDD12 pin Programmable setting of SD1 enhanced timing enable 0 1 Enhanced timing Programmable timing
Bit 3
SUSPEN_P
Power-on setting value of IDD11 pin Programmable setting of SUSPend function 0 1 Support suspend function if DMASL _P = 0 and ADV_P = 1 Support DMA transfer if DMASL _P = 0 and ADV_P = 1
Bit 2
STBY _P
Power-on setting value of IDD10 pin Programmable setting of STandBy state 0 1 W83759A is in standby state W83759A is in normal state
Bit 1
APD_P
Power-on setting value of IDD9 pin Initial setting of auto power-down 0 1 Auto power-down off Auto power-down on
Bit 0
SWAP _P
Power-on setting programming of IDD8 pin Programmable primary, secondary channel connection select 0 1 Primary channel connect to IDE1 Secondary channel connect to IDE0 Primary channel connect to IDE0 Secondary channel connect to IDE1
- 18 -
W83759A
Continued
CRX86h (ALTCTL) Bit 7
DMASL _P
Read / Write Bit 5 EMD1
DMASL _P
Alternative Control Register Bit 4 EMD0 Bit 3 PEMD1_P Bit 2 PEMD0_P Bit 1 SEMD1_P Bit 0 SEMD0_P
Bit 6 Reserved
Bit 7
Power-on setting value of VGAOEL pin. After power-on, this bit can be programmed to modify the DMA disable/enable power-on setting. 0 1 DMA mode enabled if SUSPEN_P = 0 and ADV_P = 1 DMA mode disabled
Bit 6 Bit5-4
Reserved EMD1, 0 (Read Only)
0 (default) Inverse of power-on setting value of IDEIOR , IDEIOW pin Initial setting of enhanced timing of IDE0 and IDE1 EMD1 0 0 1 1 EMD0 0 1 0 1 ATA PIO Mode 2 3 3 4 Cycle time (nS) 240 80 80 120
Bit3-2
PEMD1, 0_P
Initial setting of primary drive enhanced timing After power-on, these bits can be programmed to modify the primary drive enhanced timing. PEMD1_P PEMD0_P ATA PIO mode Cycle time (nS) 0 0 1 1 0 1 0 1 2 3 3 4 240 180 180 120
Bit1-0
SEMD1, 0_P
Initial setting of secondary drive enhanced timing After power-on, these bits can be programmed to modify the secondary drive enhanced timing SEMD1_P SEMD0_P ATA PIO Mode Cycle time (nS) 0 0 1 1 0 1 0 1 2 3 3 4 240 180 180 120
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Publication Release Date: May 1995 Revision A1
W83759A
CRX87h (REVID) Bit 7
DMASL
Read Only Bit 5 PDRV
DMASL
Revision ID Number Bit 4 SDRV Bit 3 Rev 3 Bit 2 Rev 2 Bit 1 Rev 1 Bit 0 Rev 0
Bit 6 Reserved
Bit 7
Power-on setting value of VGAOEL pin. Initial DMA enable/disable setting 0 1 DMA mode enabled if SUSPEN_P = 0 and ADV_P = 1 DMA mode disabled
Bit 6 Bit 5
Reserved (Read/Write) PDRV
0 (default) Primary channel current drive select 0 1 Master drive (default) Slave drive Master drive (default) Slave drive
Bit 4
SDRV
Secondary channel current drive select 0 1
Bit 3-Bit 0 Rev 3-Rev 0
1010b (default in A version)
- 20 -
W83759A
CRX88h (PD0TIM0)
Bit 7 PD0ACT3 Bit 6 PD0ACT2
Read/Write
Bit 5 PD0ACT1
Primary Drive0 Timing Control 0
Bit 4 PD0ACT0 Bit 3 PD0RCV3 Bit 2 PD0RCV2 Bit 1 PD0RCV1 Bit 0 PD0RCV0
Bit 7-Bit 4
PD0ACT3-0
PD0 Data Register Port (1F0h) Read/Write Active Time Read/Write active time (clocks) 0000 17/16 0001 3/2 0010 3/2 0011 4/3 0100 5/4 0101 6/5 0110 7/6 0111 8/7 1000 9/8 1001 10/9 1010 11/10 1011 12/11 1100 13/12 1101 14/13 1110 15/14 1111 16/15 PD0 Data Register Port (1F0h) Read/Write Recovery Time Write/Read recovery time (clocks) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 16/15 2/1 2/1 3/2 4/3 5/4 6/5 7/6 8/7 9/8 10/9 11/10 12/11 13/12 14/13 15/14
Bit 3-Bit 0
PD0RCV3-0
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Publication Release Date: May 1995 Revision A1
W83759A
CRX89h (PD0TIM1) Bit 7 PD0AST1 Bit 6 PD0AST0
Read/Write Bit 5 PD0DHT1 PD0AST1-0
Primary Drive0 Timing Control 1 Bit 4 PD0DHT0 Bit 3
PD0PRE
Bit 2
PD0DMA
Bit 1
PD0RDY
Bit 0 PD0ADV
Bit 7-Bit 6
PD0 Data Register Port (1F0h) Address Setup Time Read/Write extra address setup time (clocks) 00 01 10 11 0 2 2 3
Bit 5-Bit 4
PD0DHT1-0
PD0 Data Register Port (1F0h) Data Hold Time Read/Write extra data hold time (clocks) 00 01 10 11 0 2 2 3
Bit 3
PD0PRE
Prefetch/Post write control 0 1 Prefetch/Post write enabled Prefetch/Post write disabled
Bit 2
PD0DMA
PD0 DMA mode control 0 1 DMA mode enabled DMA mode disabled
Bit 1
PD0RDY
PD0 Data Register Port (1F0h) IOCHRDY Control 0 1 IOCHRDY enabled IOCHRDY disabled
Bit 0
PD0ADV
PD0 Data Register Port (1F0h) Advanced Timing Enable 0 1 Normal timing (depends on SP1, MD1, MD0 setting) Advanced timing (depends on PD0TIM1-0 setting)
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W83759A
CRX8Ah (PD1TIM0)
Bit 7 PD1ACT3 Bit 6 PD1ACT2
Read/Write
Bit 5 PD1ACT1
Primary Drive1 Timing Control 0
Bit 4 PD1ACT0 Bit 3 PD1RCV3 Bit 2 PD1RCV2 Bit 1 PD1RCV1 Bit 0 PD1RCV0
Bit 7-Bit 4
PD1ACT3-0
PD1 Data Register Port (1F0h) Read/Write Active Time Definition of these bits same as PD0ACT3-0
Bit 3-Bit 0
PD1RCV3-0
PD1 Data Register Port (1F0h) Read/Write Recovery Time Definition of these bits same as PD0RCV3-0
CRX8Bh (PD1TIM1)
Bit 7 PD1AST1 Bit 6 PD1AST0
Read/Write
Bit 5 PD1DHT1
Primary Drive 1 Timing Control 1
Bit 4 PD1DHT0 Bit 3
PD1PRE
Bit 2
PD1DMA
Bit 1
PD1RDY
Bit 0 PD1ADV
Bit 7-Bit 6
PD1AST1-0
PD1 Data Register Port (1F0h) Address Setup Time Definition of these bits same as PD0AST1-0 PD1 Data Register Port (1F0h) Data Hold Time Definition of these bits same as PD0DHT1-0
Bit 5-Bit 4
PD1DHT1-0
Bit 3
PD1PRE
PD1 Prefetch/Post write control 0 1 Prefetch/Post write enabled Prefetch/Post write disabled
Bit 2
PD1DMA
PD1 DMA mode control 0 1 DMA mode enabled DMA mode disabled
Bit 1
PD1RDY
PD1 Data Register Port (1F0h) IOCHRDY Control 0 1 OCHRDY enabled IOCHRDY disabled
Bit 0
PD1ADV
PD1 Data Register Port (1F0h) Advanced Timing Enable 0 1 Normal timing (depends on SP1, MD1, MD0 setting) Advanced timing (depends on PD1TIM1-0 setting)
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Publication Release Date: May 1995 Revision A1
W83759A
CRX8Ch (SD0TIM0)
Bit 7 SD0ACT3 Bit 6 SD0ACT2
Read/Write
Bit 5 SD0ACT1
Secondary Drive 0 Timing Control 0
Bit 4 SD0ACT0 Bit 3 SD0RCV3 Bit 2 SD0RCV2 Bit 1 SD0RCV1 Bit 0 SD0RCV0
Bit 7-Bit 4 Bit 3-Bit 0
SD0ACT3-0 SD0RCV3-0
SD0 Data Register Port (170h) Read/Write Active Time Definition of these bits same as PD0ACT3-0 SD0 Data Register Port (170h) Read/Write Recovery Time Definition of these bits same as PD0RCV3-0
CRX8Dh (SD0TIM1)
Bit 7 SD0AST1 Bit 6 SD0AST0
Read/Write
Bit 5 SD0DHT1
Secondary Drive 0 Timing Control 1
Bit 4 SD0DHT0 Bit 3
SD0PRE
Bit 2
SD0DMA
Bit 1
SD0RDY
Bit 0 SD0ADV
Bit 7-Bit 6
SD0AST1-0
SD0 Data Register Port (170h) Address Setup Time Definition of these bits same as PD0AST1-0
Bit 5-Bit 4
SD0DHT1-0
SD0 Data Register Port (170h) Data Hold Time Definition of these bits same as PD0RDHT1-0
Bit 3
SD0PRE
SD0 Prefetch/Post write control 0 1 Prefetch/Post write enabled Prefetch/Post write disabled DMA mode enabled DMA mode disabled IOCHRDY enabled IOCHRDY disabled Normal timing (depends on SP1, MD1, MD0 setting) Advanced timing (depends on SD0TIM1-0 setting)
Bit 2
SD0DMA
SD0 DMA mode control 0 1
Bit 1
SD0RDY
SD0 Data Register Port (170h) IOCHRDY Control 0 1
Bit 0
SD0ADV
SD0 Data Register Port (170h) Advanced Timing Enable 0 1
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W83759A
CRX8Eh (SD1TIM0)
Bit 7 SD1ACT3 Bit 6 SD1ACT2
Read/Write
Bit 5 SD1ACT1
Secondary Drive 1 Timing Control 0
Bit 4 SD1ACT0 Bit 3 SD1RCV3 Bit 2 SD1RCV2 Bit 1 SD1RCV1 Bit 0 SD1RCV0
Bit 7-Bit 4 Bit 3-Bit 0
SD1ACT3-0 SD1RCV3-0
SD1 Data Register Port (170h) Read/Write Active Time Definition of these bits same as PD0RCV3-0 SD1 Data Register Port (170h) Read/Write Recovery Time Definition of these bits same as PD0RCV3-0
CRX8Fh (SD1TIM1)
Bit 7 SD1AST1 Bit 6 SD1AST0
Read/Write
Bit 5 SD1DHT1
Secondary Drive 1 Timing Control 1
Bit 4 SD1DHT0 Bit 3
SD1PRE
Bit 2
SD1DMA
Bit 1
SD1RDY
Bit 0 SD1ADV
Bit 7-Bit 6 Bit 5-Bit 4 Bit 3
SD1AST1-0 SD1DHT1-0
SD1 Data Register Port (170h) Address Setup Time Definition of these bits same as PD0RCV3-0 SD1 Data Register Port (170h) Data Hold Time Definition of these bits same as PD0RCV3-0 SD1 Prefetch/Post write control 0 1 Prefetch/Post write enabled Prefetch/Post write disabled DMA mode enabled DMA mode disabled IOCHRDY enabled OCHRDY disabled Normal timing (depends on SP1, MD1, MD0 setting) Advanced timing (depends on SD1TIM1-0 setting)
SD1PRE
Bit 2
SD1DMA
SD1 DMA mode control 0 1
Bit 1
SD1RDY
SD1 Data Register Port (170h) IOCHRDY Control 0 1
Bit 0
SD1ADV
SD1 Data Register Port (170h) Advanced Timing Enable 0 1
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Publication Release Date: May 1995 Revision A1
W83759A
SYSTEM BLOCK DIAGRAM
Data Flow
IDE ATA Bus x 2 IDD VL_IDE W83759AF (100-pin)
HD
SD
IO Device
CPU
HD HD VL-Bus Chip Set W83C491/492 (160-pin x2) SD SD Super IO W83787F (100-pin)
VL_BUS
ISA Bus
Address Decode
IDE ATA Bus x 2 IDE0CS IDEA[2:0] VL_IDE W83759AF (100-pin)
IDE1CS
HA LDEV
SA
IO Device
CPU
HA HA VL-Bus Chip Set W83C491/492 (160-pin x2) SA SA Super IO W83757 W83787F (100-pin)
LDEV VL_BUS
ISA Bus
- 26 -
W83759A
Control Signal
IDE ATA Bus x 2
IDEIOR, IDEIOW
IDEIOR, IDEIOW
IORDY
LADS, ... *
LDEV, LRDY
VL_IDE W83759AF (100-pin)
XIOR XIOW XIOR
IO Device
CPU
RDYRTN VL-Bus Chip Set W83C491/492 (160-pin x2) XIOR XIOW
XIOW
LADS,... LDEV, LRDY
Super IO W83787F (100-pin)
RDYRTN VL_BUS ISA Bus
* LADS,... = LADS, HMIO, HWR, HDC, BE2, BE0
FUNCTION BLOCK DIAGRAM
LCLK SYSRST LADS RDYRTN SP1, MD1, MD0 Command Enable HA[9:2] BE2, BE0 SA1, SA0, AEN HMIO, HWR, HDC VGAOEH, VGAOEL XIOR, XIOW
TIMING REGISTERS MUX
CONTROL LOGIC
LRDY LDEV
1f0 32 16 /170 Bit Bit
IORDY
IDEA[2:0] IDE0CS1 IDE0CS0 IDE1CS1 IDE1CS0 IDEIOR IDEIOW
DECODE LOGIC PREFETCH CONTROL
Data Flow Control
HD[31:0]
DATA BUFFER
ID[15:0] SD[7:0]
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Publication Release Date: May 1995 Revision A1
W83759A
FUNCTIONAL DESCRIPTION
Reset Initialization
The CPU clock rate, hard disk access time, hard disk controller enable, and hard disk I/O select are latched at the rising edge of SYSRST . These values are used to control the host and drive access signal timing. Additionally, the W83759A is initialized to a known state by an active low on SYSRST. Any operation in progress is immediately terminated by SYSRST .
Host in Terface
The W83759A operates as a slave device, responding only to cycles within the host I/O address space. The IDE drive data port at address 1F0h (170h) is a 16-bit port that requests a double-word data transfer at address 1F0h (170h). All byte swapping, conversion, word, and double-word assembly are done at the host interface. Table 1 summarizes the W83759A host interface cycle decoding. Table 1. W83759A Cycle Definition HMIO 0 0 0 0 HDC 1 1 1 1 HWR 0 1 0 1 ADDRESS SPACE 1F0h-1F7h and 3F6h 1F0h-1F7h and 3F6h 170h-177h and 376h 170h-177h and 376h HOST BUS CYCLE I/O Read I/O Write I/O Read I/O Write W83759A CYCLE IDE0 Read Cycle IDE0 Write Cycle IDE1 Read Cycle IDE1 Write Cycle
a. CPU WRITE CYCLES Table 2. W83759A Write Data Operation BYTE ENABLE
BE3 BE2 BE1 BE0
W83759A INPUT DATA HD[31:16] x x x x x Valid HD[15:0] x x x x Valid Valid SD[7:0] Valid Valid Valid Valid x x
I/O ADDRESS
1 1 1 0 1 0
1 1 0 1 1 0
1 0 1 1 0 0
0 1 1 1 0 0
1F1-1F7 (171-177)
1F0 (170)
8-bit IDE Write Data Path: CPU Valid HD Byte SD[7:0] W83759A ID[7:0] 16/32-bit IDE Write Data Path: CPU Valid HD Word W83759A ID[15:0]
- 28 -
W83759A
b. CPU READ CYCLES Table 3. W83759A Read Data Operation BYTE ENABLE
BE3 1 BE2 1 BE1 1 BE0 0
W83759A OUTPUT DATA HD[31:16] HD[15:0] SD[7:0] x x x x x Valid x x x x Valid Valid Valid Valid Valid Valid x x
I/O ADDRESS 1F1-1F7 (171-177)
1 1 0 1 0
1 0 1 1 0
0 1 1 0 0
1 1 1 0 0
1F0 (170)
8-bit IDE Read Data Path: CPU Valid HD Byte Chip Set SD[7:0] W83759A ID[7:0] 16/32-bit IDE Read Data Path: CPU Valid HD Word W83759A ID[15:0]
Drive Interface
The W83759A is designed to work with standard IDE disk drives. For the IDE interface, the W83759A provides a 16-bit data path ID[15;0], address lines IDEA[2:0], decoded device select signals IDE0CS0 (IDE1CS0) and IDE0CS1 ( IDE1CS1), and decoded command sigals IDEIOR and IDEIOW . During normal operation, the drive address outputs IDEA[2:0] are used to select a register in an IDE drive. These addresses are generated from BE2 , BE0 , HA2 and SA1, SA0. Table 4 summarizes the type enable decoding for normal operation. Table 4. IDEA[2:0] Generation HA2 0 0 0 0 0 1 1 1 1
BE2 1 BE0 0
SA1 x x 0 1 1 0 0 1 1
SA0 x x 1 0 1 0 1 0 1
IDEA[2:0] 000 000 001 010 011 100 101 110 111
I/O ADDRESS 1F0 (170) 16-bit 1F0 (170) 32-bit 1F1 (171) 1F2 (172) 1F3 (173) 1F4 (174) 1F5 (175) 1F6 (176) 1F7 (177)
0 x x x x x x x
0 x x x x x x x
Two drive chip select signals, IDE0CS0 ( IDE1CS0 ) and IDE0CS1 ( IDE1CS1), are generated from the local bus addresses and ISA bus address. The 16-bit data register may be read or written at I/O address 1F0h(170h). The 8-bit IDE command and status registers are at I/O addresses 1F1h through 1F7h (and 171h through 177h). The IDEIOR or IDEIOW commands are generated for all address
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Publication Release Date: May 1995 Revision A1
W83759A
regions in which IDE0CS0 ( IDE1CS0 ) and IDE0CS1 ( IDE1CS1) are active. Table 5 summarizes the decoding of these sgnals. Table 5. Drive Select Signal Operation SELECT SIGNAL
IDE0CS0 IDE0CS1 IDE1CS0 IDE1CS1
ADDRESS RANGE I/O Address 1F0h through 1F7h I/O Address 3F6h I/O Address 170h through 177h I/O Address 376h
IDE Timing Control
Pin SP1 is used to set the VL-Bus speed. The IDE drive interface will maintain the same ATA PIO timing parameters for IDE drive 16-bit IO access cycles (1F0/170) regardless of whether the VL-Bus operates at 33 or 50 MHz. In W83759 mode, IDE drive timing is controlled by pins MD1 and MD0, which are used to select the IDE drive PIO mode 0-2. The drive timing depends on the ATA specification for the IDE drive PIO mode selected. In W83759A mode, IDE drive timing is controlled by pins EMD1 and EMD0, which are used to select the IDE drive PIO mode 2-4. The drive timing depends on the ATA specification for the IDE drive PIO mode selected. Table 6 summarizes the ATA Rev. 4.0 and ATA-2 PIO timing parameters. Table 7 and Table 8 summarize the W83759A PIO read/write command pulse and cycle timing when a 16-bit IDE IO access is performed. Because 8-bit IDE IO accesses are always passed to the ISA bus, the W83759A transceives data through the ISA data bus and induces IDE read/write commands from ISA XIOR / XIOW . Thus the 8-bit command timing will always meet ATA timing specifications. Table 6. ATA Rev. 4.0 and ATA-2 PIO Minimum Timing Parameters ATA PIO 8/16-bit IO access 16-bit 8-bit MODE 4 Active Pulse 60 60 Cycle Time 120 120 MODE 3 Active Pulse 80 80 Cycle Time 180 180 MODE 2 Active Pulse 100 290 Cycle Time 240 290 MODE 1 Active Pulse 125 290 Cycle Time 383 383
Unit: nS
MODE 0 Active Pulse 165 290 Cycle Time 600 600
Unit: LCLK
Table 7. PIO Command Pulse and Cycle Timing (W83759 mode) SP1 0 0 MD1 0 0 MD0 0 1 IDE WRITE ACTIVE PULSE 6 (180) 6 (180) IDE READ ACTIVE PULSE 7 (210) 7 (210) READ/WRITE CYCLE TIME 22 (660) 19 (570)
IDE MODE SELECT Mode 0 Mode 0+
- 30 -
W83759A
Table 7. PIO Command Pulse and Cycle Timing, continued
SP1 0 0 1 1 1 1
MD1 1 1 0 0 1 1
MD0 0 1 0 1 0 1
IDE WRITE ACTIVE PULSE 8 (240) 4 (120) 9 (180) 9 (180) 7 (140) 6 (120)
IDE READ ACTIVE PULSE 9 (270) 5 (150) 10 (200) 10 (200) 8 (160) 7 (140)
READ/WRITE CYCLE TIME 13 (390) 9 (270) 31 (620) 27 (540) 19 (380) 13 (260)
IDE MODE SELECT Mode 1 Mode 2 Mode 0 Mode 0+ Mode 1 Mode 2
Note: It is recommended that SP be set to 0 when LCLK is 33 MHz. The initial default value is SP1 = 0. The timing value (nS) is based on LCLK = 20 nS when SP1 = 1 and LCLK = 30 nS when SP1 = 0.
Table 8. PIO Command Pulse and Cycle Timing (W83759A mode) SP1 0 0 0 0 1 1 1 1 EMD1 0 0 1 1 0 0 1 1 EMD0 0 1 0 1 0 1 0 1 IDE WRITE ACTIVE PULSE 4 (120) 3 (90) 3 (90) 2 (60) 4 (80) 4 (80) 3 (60) 2 (40) IDE READ ACTIVE PULSE 5 (150) 4 (120) 4 (120) 3 (90) 5 (100) 5 (100) 4 (80) 3 (60) READ/WRITE CYCLE TIME 8 (240) 6 (180) 6 (180) 4 (120) 11 (220) 9 (180) 7 (140) 5 (100)
Unit: LCLK
IDE MODE SELECT Mode 2 Mode 3 Mode 3 Mode 4 Mode 2 Mode 3 Mode 4Mode 4+
Note: It is recommended that SP be set to 0 when LCLK is 33 MHz. The initial default value is SP1 = 0. The timing value (nS) is based on LCLK = 20 nS when SP1 = 1 and LCLK = 30 nS when SP1 = 0.
Prefetch Control
The W83759A IDE command prefetch feature provides concurrent operations by pipelined readahead of the next data word(s) from the drive while the host is transferring previously requested disk data into system memory. This reduces the amount of time that the host must pause and wait for data to be accessed. While the host is writing data to memory, the W83759A reads data from the disk drive. As soon as the host reads the W83759A data, new data are requested by the W83759A from the disk drive. This prefetch feature is active only for disk data at the 1F0h and 170h IO addresses and does not oprate on other disk register data.
Power-saving Control
The W83759A provides three power-saving modes. In the initial-level power-saving mode, all of the drive's control, address, data, and other signals enter a logic 1 standby state when no IDE disk cycle is active. This reduces unnecessary power use and decreases the amount of EMI radiation generated by driving the long IDE cable continuously.
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Publication Release Date: May 1995 Revision A1
W83759A
After power on, the W83759A automatically enters the "Auto-Power-Down" (APD) mode. In this mode the only active logic inside the W83759A is the host address decoder and bus tracking state machine. Power is saved by not switching logic inside the W83759A that is not being utilized. Whenever an IDE transfer cycle is detected, the W83759A leaves APD mode and the entire chip becomes active. The W83759A enters APD mode again after the completion of an IDE transfer cycle. To support deep-green systems, the W83759A also provides advanced power saving modes, standby mode, and suspend mode. When standby mode is enabled ( STBY bit goes low), all of the logic inside the W83759A is stopped until standby mode is disabled ( STBY bit goes high). When suspend mode is enabled (SUSPEN bit goes high and DMASL is low on SYSRST rising), the W83759A will enter suspend state when SUSP goes low and return to normal state when SUSP goes high.
ABSOLUTE MAXIMUM RATINGS
(VDD = 5 V 5%, VSS = 0V )
PARAMETER Power Supply Voltage Input Voltage Operating Temperature (Ta) Storage Temperature
RATING -0.3 to 7.0 VSS-0.3 to VDD +0.3 0 to + 70 -55 to + 150
UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC CHARACTERISTICS
(TA = 0 C to +70 C, VDD = 5V 5%, VSS = 0V)
PARAMETER Input Low Voltage Input High Voltage Input High Leakage with Pull-Down Input Low Leakage with Pull-Up Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage Input Capacitance Output Capacitance
SYM. VIL VIH ILIHD ILILU ILIH ILIL VOL VOH CIN COUT
CONDITIONS
MIN. -0.3 2.0
MAX. 0.8 VDD + 0.3 +500 -500 +10 -10 0.4 VDD 5 10
UNIT V V A A A A V V pF pF
VIN = VDD VIN = 0V VIN = VDD VIN = 0V IOL = 8 mA ( LDEV , SD, IDE pins) IOL = 6 mA (other pins) IOL = -8 mA (LDEV , SD, IDE pins) IOL = -6 mA (other pins)
2.4 -
- 32 -
W83759A
DC Characteristics, continued
PARAMETER Operating Current Standby Current
SYM. IDD ISTBY
CONDITIONS FLCLK = 50 MHz All input and I/O pins pulled high, LCLK = VDD
MIN. -
MAX. 25 800
UNIT mA A
AC CHARACTERISTICS
All AC timing is measured from the 0.8V and 2.0V on the source signal to the 0.8V and 2.0V level on the signal under test. AC specifications are given for the following testing conditions: VDD = 5V 5%, Temp. = 0 C to 70 C VL-Bus shared signal loading = 100 pF VL-Bus non-shared signal loading = 33 pF ISA Bus signal loading = 240 pF IDE device interface loading = 30 pF SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 PARAMETER LCLK Period LCLK High Time LCLK Low Time SYSRST Pulse Width POS Pin to SYSRST Setup Time POS Pin Hold Time from SYSRST LADS to LCLK Setup Time LADS Hold Time from LCLK LDEV Active Delay from Address VESA IO Read Host Data Drive Delay HMIO, HDC , HWR to LCLK Setup Time when LDEV asserted at T2 HMIO, HDC , HWR to LCLK Setup Time when LDEV asserted at T2 LRDY Active Delay from LCLK LRDY Inactive Delay from LCLK RDYRTN to LCLK Setup Time RDYRTN Hold Time from LCLK VESA IO Write Host Data Valid Delay VESA IO Write Host Data Hold Time MIN. 20 5 5 16 200 10 6 3 39 5 5 10 5 6 6 3 0 16 16 18 20 MAX. UNIT nS nS nS LCLK nS nS nS nS nS nS nS nS nS nS nS nS nS nS FIG. Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 1 Fig. 2 Fig. 2 Fig. 2 Fig. 2, 4 Fig. 2, 3 Fig. 2, 3 Fig. 2, 3 Fig. 2, 3 Fig. 2, 3 Fig. 2, 3 Fig. 3 Fig. 3, 5
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Publication Release Date: May 1995 Revision A1
W83759A
AC Characteristics, continued
SYMBOL t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 t43 t44 t45
PARAMETER IDEA[2:0] Valid Delay from Address Valid IDEA[2:0] Invalid Delay from Address Change
IDE0CS0 , IDE1CS0 Valid Delay from Address valid IDE0CS0 , IDE1CS0 Invalid Delay from Address Change
MIN. 5 5 0 10 10 5 4 8 5 8 30 -
MAX. 18 18 18 18 22 24 16 30 20 30 20 20 17 17 18 18 16 20 16 20 20 20 20 20
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
FIG. Fig. 4, 5 Fig. 4, 5 Fig. 4, 5 Fig. 4, 5 Fig. 4, 5 Fig. 4, 5 Fig. 4 Fig. 4 Fig. 4 Fig. 5 Fig. 5 Fig. 6, 7 Fig. 6, 7 Fig. 6, 7 Fig. 6, 7 Fig. 6 Fig. 6 Fig. 7 Fig. 7 Fig. 8 Fig. 8 Fig. 9 Fig. 9 Fig. 6 Fig. 6 Fig. 7 Fig. 7
IDEIOR, IDEIOW Active Delay from LCLK
IDEIOR , IDEIOW Inactive Delay from LCLK IDE Read IDD Data Hold Time from LCLK IDE Read IDD to HD Delay IDE Read HD Float Delay from LCLK IDE Write IDD Drive Delay IDE Write IDD Float Delay IDEA[2:0] Valid Delay from A2 SA[1:0] Valid IDEA[2:0] Invalid Delay from A2 SA[1:0] Change
IDE0 CS1, IDE1CS1 Valid Delay from Address Valid
IDE0CS1, IDE1CS1 Invalid Delay from Address Change ISA IDE Read IDD to SD Delay ISA IDE Read IDD Data Hold Time from IDEIOR ISA IDE Write SD to IDD Delay ISA IDE Wrtie SD Data Hold Time from XIOW VGA Read IDD to HD Delay
VGA Read HD Float Delay from VGAOEL VGA Write HD to IDD Delay VGA Write HD Float Delay from VGAOEH ISA IDD Read IDEIOR Active Delay from XIOR ISA IDD Read IDEIOR Inactive Delay from XIOR ISA IDE Write IDEIOW Active Delay from XIOW ISA IDE Write IDEIOW Inactive Delay from XIOW
- 34 -
W83759A
TIMING WAVEFORMS
All AC timing is measured from the 0.8V and 2.0V on the source signal to the 0.8V and 2.0V level on the signal under test.
LCLK, SYSRST , Timing
t1 LCLK SYSRST ENIDE, TEST SP1, MD1, MD0 PRDYEN, SRDYEN IDD[15:0], EMD1, EMD0 DMASL t4 t2 t3
t5
t6
Figure 1 Note: ENIDE, TEST, SP1, MD1, MD0, PRDYEN, SRDYEN, IDD[15:0], EMD1, EMD0, DMASL are POS (Power-On Setting) pins. When SYSRST is low they are tri-stated as inputs.
VESA IO Read Timing
Local IDE Time T1 LCLK
t7 t8
T2
LADS HA[9:2], BE2, BE0 HMIO = 0 HDC = 1 HWR = 0 LDEV
t10
t11
t12
t9
HD[31:0]
t13 t14
LRDY
t15 t16
RDYRTN
Figure 2 Note: Local IDE cycle time is determined by SP1, MD1, and MD0 or by SP1, EMD1 and EMD0 at power-on. After power-on the driver can program the timing register to tune the timing.
- 35 -
Publication Release Date: May 1995 Revision A1
W83759A
VESA IO Write Timing
Local IDE Cycle Time
T1 T2
LCLK
t7 t8
LADS HA[9:2], BE2, BE0
t11
HMIO = 0 HDC = 1 HWR = 1
t9
t12
LDEV
t18
t17
HD[31:0]
t13 t14
LRDY
t15 t16
RDYRTN
Figure 3
- 36 -
W83759A
IDE IO Read Timing
Local IDE Cycle Time
T1 T2
LCLK LADS LDEV HA[9:2], BE2, BE0
t19 t20
IEDA[2:0]
t21
IDE0CS0 IDE1CS0
Recovery Time Pulse Width t23 t24
t22
IDEIOR
t25
IDD[15:0]
t10 t26 t27
HD[31:0]
LRDY RDYRTN
Figure 4 Note: At power-on the recovery time and pulse width are determined by SP1, MD1, and MD0, or by SP1, EMD1 and EMD0 as indicated in Table 7. and Table 8. After power-on the driver can program the timing register to tune the timing. Example: When SP = 1 and MD1 = MD0 = 0, the IDEIOR pulse width is 10 LCLK and recovery time is 21 LCLK (cycle time is 31 LCLK).
- 37 -
Publication Release Date: May 1995 Revision A1
W83759A
IDE IO Write Timing
Local IDE Cycle Time
T1 T2
LCLK LADS LDEV HA[9:2], BE2, BE0
t19 t20
IEDA[2:0]
t21
IDE0CS0 IDE1CS0
Recovery Time Pulse Width t23 t24
t22
IDEIOW
t18
HD[31:0]
t28 t29
IDD[15:0]
LRDY RDYRTN
Figure 5 Note: At power-on the recovery time and pulse width are determined by SP1, MD1, and MD0 or by SP1, EMD1, and EMD0 as indicated in Table 7 and Table 8. After power-on the driver can program the timing register to tune the timing. Example: When SP = 1 and MD1 = MD0 = 0, the IDEIOW pulse width is 9 LCLK and recovery time is 22 LCLK (cycle time is 31 LCLK).
- 38 -
W83759A
ISA IO Read Timing
SA1, SA0 AEN
t30 t31
IDEA[1:0]
t32
IDE0CS1, IDE1CS1 XIOR IDEIOR
t42 t43
t33
t35
IDD[7:0]
t34
SD[7:0]
Figure 6
ISA IO Write Timing
SA1, SA0 AEN
t30 t31
IDEA[1:0] IDE0CS1, IDE1CS1 XIOW IDEIOW
t44 t45 t32 t33
t37
SD[7:0]
t36
IDD[7:0]
Figure 7
- 39 -
Publication Release Date: May 1995 Revision A1
W83759A
VGAOEL Read Timing
HWR
VGAOEL
IDD[15:0]
HD[15:0]
Figure 8
VGAOEH Write Timing
HWR VGAOEL
HD[31:16]
t40 t41
IDD[15:0]
Figure 9
- 40 -
W83759A
PACKAGE DIMENSION
100-pin QFP
Dimension in inches Dimension in mm
Symbol
HD D
100 81
Min. Nom
0.004 0.107 0.010 0.004 0.546 0.782 0.020 0.728 0.964 0.039 0.087 0.112 0.012 0.006 0.551 0.787 0.026 0.740 0.976 0.047 0.094
Max.
0.130
Min. Nom
0.10
Max.
3.30
1
80
EH
E
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
0.117 0.016 0.010 0.556 0.792 0.032 0.752 0.988 0.055 0.103 0.004
2.73 0.25 0.10 13.87 19.87 0.50 18.49 24.49 1.00 2.21
2.85 0.30 0.15 14.00 20.00 0.65 18.80 24.80 1.20 2.40
2.97 0.40 0.25 14.13 20.13 0.80 19.10 25.10 1.40 2.62 0.10
0
12
0
12
30
51
31
e
b
50
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
c
AA
1
2
See Detail F Seating Plane
y
A
L L1
Detail F
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 41 -
Publication Release Date: May 1995 Revision A1

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